We’ve heard so much about the CXL interconnect – including the recent announcement of CXL v3.0 – and components that are CXL-ready, that it may come as a surprise that CXL v1.1 “hosts” are only just now shipping. It’s a technology that could play a central role in the ever-more heterogenous, more memory-intensive systems of the future. And now, after several years of experimentation and various interconnect consortia, CXL is emerging as the standard for advanced functionality for fabric technologies. Along with CXL we also discuss some of the details of the CHIPS and Science Act….
PNNL and Micron Partner to Push Memory Boundaries for HPC and AI
March 8, 2022 by
Researchers at Pacific Northwest National Laboratory (PNNL) and Micron are are developing an advanced memory system to support AI for scientific computing. The work is designed to address AI’s insatiable demand for live data — to push the boundaries of memory-bound AI applications — by connecting memory across processors in a technology strategy utilizing the […]
Astera Labs Claims 1st CXL 2.0 Memory Accelerator SoC Platform
November 15, 2021 by
SANTA CLARA, CA, U.S. – November 15, 2021 – Astera Labs, make of connectivity solutions for intelligent systems, today announced its new Leo Memory Accelerator Platform for Compute Express Link (CXL) 1.1/2.0 interconnects to enable disaggregated memory pooling and expansion for processors, workload accelerators, and smart I/O devices. Leo overcomes processor memory bandwidth bottlenecks and […]
